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how to avoild charging damage in IC manifacturing

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HOW TO AVOID CHARGING DAMAGE IN IC MANUFACTURING Wes Lukaszek Wafer Charging Monitors, Inc. 127 Marine Road, Woodside, CA 94062 USA Wafer charging damage during IC processing is the result of complex interactions between the wafer environment and the wafer. Understanding these interactions, and recognizing the relative importance of the different mechanisms capable of causing damage, are essential for successful diagnosis and control of charging damage during wafer manufacturing. This paper presents a unif perspective of charging damage in IC manufacturing, and from it derives a set of guidelines which can be used by equipment and IC manufacturers to avoid charging damage to ICs during wafer processing. INTRODUCTION Charging damage during wafer processing is often perplexing, as evident from the countless papers that have been written about it during the last twenty years. However, when we look for the fundamentals behind charging damage, we find a single underlying cause: charge trapping in SiO 2 near device space charge regions. This single cause is responsible for all of the observed device effects, including threshold voltage shifts, transconductance degradation, enhanced junction leakage, etc. Since charge trapping is a consequence of charge transport through the affected SiO 2 regions [1], the process phenomena responsible for charging damage can be inferred from the basic physical mechanisms governing charge transport in SiO2 . The two mechanisms responsible for charge conduction in SiO 2 are: (a) electron tunneling through the SiO 2 potential barrier, illustrated in Figure 1, which requires very high electric fields in the SiO 2 [1], and (b) charge transport over the SiO 2 potential barrier, illustrated in Figures 2a and 2b, which occurs even at low electric fields in the presence of UV light [2]. The mechanism illustrated in Figure 2a, in which electrons from the conduction or valence band of silicon are excited to the conduction band of the SiO 2 , and subsequently transported by electric fields in the SiO 2 , occurs at photon energies greater than 3.2 eV (388 nm), but lower than ~9 eV (138 nm). At these photon energies, the SiO 2 is transparent to UV, so this mechanism can affect device structures located deep under the surface of the wafer. At photon energies greater than ~ 9 eV, the SiO 2 becomes conductive due to the mechanism shown in Figure 2b, where UV breaks SiO 2 bonds, creating electron-hole pairs. Although photons with energies greater than ~ 9 eV are rapidly absorbed in the SiO 2 and the electron- hole pairs are produced at the surface of the wafer, they become separated and transported to device structures by the electric fields which may be present in the SiO 2 . Page 1 of 9 © Copyright 2004, Wafer Charging Monitors, Inc., All rights reserved

how to avoild charging damage in IC manifacturing

ee- e- h+ (a) Figure 1. Charge transport at very high electric field (tunneling). (b) Figure 2. UV-enabled charge transport: (a) 3.2 eV < h? < 9 eV; (b) h? > 9 eV Consequently, since surface charging produces the electric fields responsible for charge transport, it is apparent that in high UV environments surface charging is not acceptable. In processes where UV intensity is very low, some wafer surface charging may be tolerated, provided it is not sufficient to cause the high electric fields required by the electron tunneling mechanism illustrated in Figure 1. Regardless of which device parameters are affected, these are the underlying basics of charging damage. However, the implications they carry depend on the process tools, processes, and device types in question. We will next discuss processes typically responsible for charging damage. OXIDE DEPOSITION During plasma oxide depositio n, when the entire wafer surface is exposed to intense UV, even low levels of wafer charging can cause damage. Consequently, plasma oxide depositions are often troublesome processes in wafer manufacturing. Several causes contribute to this. The principal reason for gate oxide damage is the huge reduction in the breakdown charge (Q bd ) of the oxide. At the high deposition temperature – typically around 400 o C – the breakdown charge of the oxide is reduced by several orders of magnitude [3]! This drastically reduces the amount of oxide current that needs to be collected by electrodes connected to transistor gates in order to cause transistor damage. This current is readily suppl by relatively low levels of surface charging when the oxide becomes conductive due to the intense UV. During the early stage of deposition, when topographical features are prominent on the surface of a wafer, it may be possible that the “electron shading” mechanism (discussed later) also contributes to the observed damage [4]. However, as the deposition proceeds, trenches become filled, reducing the magnitude of this effect. Moreover, this mechanism cannot explain the increase in damage with increasing deposition. Consequently, it is safe to conclude that the primary cause of charging damage during oxide deposition is the UV-enabled conduction mechanism: UV generates the charges that are then transported to different device structures with the help of the electric field established by surface charging. Moreover, it is observed that when surface charging is Page 2 of 9 © Copyright 2004, Wafer Charging Monitors, Inc., All rights reserved

how to avoild charging damage in IC manifacturing

eliminated by making the deposition plasma uniform, charging damage is eliminated – even though the intense UV is still present [5]. It should be noted that gate oxide damage is not the only form of device damage possib le under these conditions. Other types of damage (i. e., device parameter shifts) are also possible when charges are transported to, and trapped near, device space charge regions. Among them are: increased junction leakage, increased source-drain leakage, beta degradation in bipolar transistors, etc. Consequently, to avoid charging damage during oxide depositions, surface charging must be completely eliminated. EFFECT OF UV AND CHARGING ON NON-VOLATILE ICs A different symptom of the cooperative effect between UV and surface charging was observed during manufacture of floating- gate non-volatile memory devices [6,7]. Here, charge conduction in SiO 2 , caused by UV and elevated positive potentials around wafer periphery, shown in Figure 3a, led to charge trapping on EPROM transistor floating- gates during via etch, equivalent to EPROM programming. During forming gas anneal, the electric field in the SiO 2 surrounding the floating- gates led to the formation of positive traps via the NBTI mechanism [8,9]. The positive traps, in turn, caused chargeloss from the floating gates during charge-storage tests, evident from threshold voltage margin instabilities around wafer periphery, as shown in Figure 3b. The role of UV in this case was unmistakable, since changes in the gas mixture used during the via etch showed a significant influence on UV intensity and the observed charge- loss. By reducing the amount of CO in the gas mixture, it was possible to eliminate the threshold voltage margin instability [6]. At the same time, changes in the gas mixture had no effect on the level of surface charging, so the disappearance of the threshold voltage margin instability was clearly due to change in the spectrum and intensity of UV. This mechanism was confirmed by programming EPROMs on a tester over the entire wafer, and then subjecting the wafers to a forming gas anneal. All die whose EPROMs were programmed on the tester to a high V t state failed the threshold voltage margin instability test, as shown in Figure 3c. Figure 3a. Positive potentials during via etch. Figure 3b. Die around periphery fail margin tests (black = fail). Figure 3c. Programmed die fail margin tests after forming gas anneal. Page 3 of 9 © Copyright 2004, Wafer Charging Monitors, Inc., All rights reserved

how to avoild charging damage in IC manifacturing

ETCHING PLASMAS – “ELECTRON SHADING” EFFECT Plasmas that are uniform1 over the entire surface of a wafer do not cause surface charging, and thus would appear to eliminate damage from the electron tunneling mechanisms, as well as from the cooperative effect of UV and surface charging. However, during etching, a feature-size-dependent “electron shading” mechanism causes localized charging at the bottom of the holes of etched features [10]. This effect is due to the anisotropic ion flux2 used in etching plasmas and the isotropic electron flux. As illustrated in Figure 4, the isotropic electron flux charges negatively the inside top of narrow resist holes (or lines) thereby setting up a potential barrier to entry of electrons. Since electrons cannot enter the holes and neutralize the ion flux, positive charging results at the bottom of the resist holes. Conversely, in regions where the resist spacing is wide electrons can enter the holes, setting up a negative potential. The combination of high positive potentials in some regions of a die, and negative potentials in other regions of a die creates the equivalent of an intra-die plasma non-uniformity, causing charge flow through the gate oxides of transistors, thereby creating damage. Making the plasma uniform minimizes this effect, but does not eliminate it, as shown in Figure 5a. However, the intensity of charging due to this mechanism is greatly increased in non- uniform plasmas, as illustrated in Figure 5b [11]. Consequently, etching plasmas must be made uniform to minimize the “electron shading” effect and thus minimize device damage. ion flux electron flux current flow Figure 4. The anisotropic ion flux and isotropic electron flux in etching plasmas cause positive charging at the bottom of narrow trenches, and negative charging at the bottom of wide trenches. Figure 5a. Uniform plasma produces uniform positive charging over entire wafer in 0.5 um holes (in 1.2 um resist). 1 2 Figure 5b. Non-uniform plasma produces non-uniform, and greatly enhanced, positive charging (note J scale change). Meaning, that electron and ion fluxes are equal at every point on the wafer. Produced by the application of RF bias to the wafer. Page 4 of 9 © Copyright 2004, Wafer Charging Monitors, Inc., All rights reserved

how to avoild charging damage in IC manifacturing

EFFECT OF SUBSTRATE ANTENNAS To prevent charging damage from “electron shading”, the size of chargecollecting “antennas” connected to transistor gates is limited during circuit design. However, recent work [12,13,14] indicates that the size of charge-collecting “antennas” connected to wafer substrate exerts a significant effect on surface potentials and charging currents sensed by “antennas” connected to transistor gates: the smaller the area of the “antennas” connected to the substrate, the greater the charging experienced by the “antennas” connected to trans istor gates, as illustrated in Figure 6. Consequently, in addition to enforcing gate “antenna” design rules, efforts should me made to maximize the area of the “antennas” connected to wafer substrate. large antenna medium antenna small antenna Figure 6. Positive charging measured on identical antennas connected to transistor gates increases (J-V plots move to higher voltages) when the size of antennas connected to wafer substrate decreases. ION IMPLANTATION Control of wafer charging in ion implanters is governed by an entirely different set of rules. Since UV intensity in ion implanters is typically very low, charging damage during ion implantation results only from electron tunneling through the SiO 2 potential barrier, which requires very high electric fields in the SiO 2 . The high potentials on wafer surface required to produce these electric fields result from the beam ions and (primarily) from escaping secondary electrons, which produce positive potentials on the surface of a wafer when a device is under the beam. To neutralize this positive charging, electron “showers” or Plasma Flood Systems (PFS) are employed. However, the electrons from the electron “shower” or a PFS also produce negative charging when a device is outside the beam. Increasing the electron output from the electron “s hower” or PFS increases the negative potentials, and decreases the positive potentials. The opposite is true when the output from the electron “shower” or PFS is reduced. Consequently, control of wafer charging in ion implanters is a matter of balance between positive charging, and negative charging, as illustrated in Figures 7a-7b. Page 5 of 9 © Copyright 2004, Wafer Charging Monitors, Inc., All rights reserved

how to avoild charging damage in IC manifacturing

Positive J-V Plots Negative J-V Plots Figure 7a. High positive charging is observed during a high current implant when PFS is turned OFF. Positive J-V Plots Negative J-V Plots Figure 7b. Positive charging is reduced (positive J-V plots move to lower voltages) and negative charging is increased (negative J-V plots move to higher voltages) during the same implant when PFS is turned ON. Since the high current densities encountered during positive charging [15] can be potentially very destructive, there exists a historical fear of positive charging, and a tendency to “over- flood” implants1 . However, since charging occurs in sub- millisecond pulses, deep-depletion of the substrate, and reverse-biased wells, provide protection by absorbing a major fraction of the appl potentials. A straight- forward device analysis shows that most vulnerable are N-channel trans istor during negative charging, when the full negative potentials are appl across the gate oxide [16]. Consequently, electron showers or PFS’ should be used only to bring positive charging under sufficient control so it does not overwhelm the protection provided by the transistor depletion regions and 1 That is, to generate more negative charge with the electron shower or PFS than is really necessary. Page 6 of 9 © Copyright 2004, Wafer Charging Monitors, Inc., All rights reserved

how to avoild charging damage in IC manifacturing

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